Voltage to frequency converters (VFCs) are a preferred technique of noise-tolerant analog to digital conversion. Synchronous VFCs (just like the Analog Units AD652) wherein an exterior, often crystal-derived, clock offers timing for the conversion course of, have important efficiency benefits (pace, linearity, precision impartial of passive parts) over the free-running kind wherein conversion timing should in the end depend on an RC time fixed.
However a attribute limitation of all VFCs, each synchronous and asynchronous, is that they make comparatively gradual analog-to-digital converters (ADCs) as a result of the full-scale output frequency, and subsequently conversion pace for any given conversion decision, is restricted by the analog switches used within the conversion course of wherein pace and precision are inherently inversely associated. This design thought (Determine 1) pushes most correct working frequency past 1 MHz by using high-speed H-CMOS logic gadgets as extraordinarily quick analog switches.
Determine 1 The excessive pace synchronous VFC.
Right here’s the way it works:
D-type flip-flop #1 (FF#1) within the HC74 varieties a suggestions loop with op-amp #2 within the 6482 appearing as a high-resolution comparator and with the excessive pace (~ns transition occasions) of the HC74 switches appearing to use 0/5V to Q1 based on the 0/1 state of the op-amp output when the FF is clocked. The responsibility cycle (DC1) of the FF is thus time averaged by R1C3 and servoed by the suggestions loop to power VR1C3 = 5V * DC1 = Vin and DC1 = Vin / 5V. However a logic provide is usually a poor alternative for a conversion reference voltage, so if this had been all there was to the story, expectations for VFC accuracy would likewise be poor. We want a trick to compensate for the inevitable inaccuracy and noise within the +5V provide.
The wanted compensation is offered by FF#2 implementing one other suggestions loop.
FF#2 is linked to kind a monostable (one-shot) triggered by Fclk, making use of 5V pulses to the R4C4 averaging community with pulse length (Tp) decided by R2, R3, C1 community and op-amp #1. The voltage is averaged by VR4C4 = Fclk * 5V * Tp. Op-amp #1 compares this common to Vref and forces Tp in order that Tp = Vref / Fclk / 5V. As a result of each FFs occupy the identical chip, accuracy-affecting parameters like propagation delays, transition occasions, and voltage offsets might be very comparable and monitor effectively over temperature and provide voltage variations, making compensation very efficient.
These T length pulses turn into the clock reference for FF#1, thus…
DC1 = Fout * Tp / Fclk = Fout * Vref / Fclk / 5V = Vin / 5V
…yielding (lastly) the hoped-for classical synchronous VFC conversion equation…
Fout / Fclk = Vin / Vref
The ensuing VFC has some helpful traits apart from excessive pace (for a VFC). This features a good linearity, a tolerance of Vref within the vary of 1 to 4 V, Fclk from 500 kHz to three MHz, operation from a single “5V+”, a 3 to six V provide, a low energy consumption (~10 mW), very excessive enter impedances (e.g., lower than 1pA enter present on Vin and Vref), and no important or high-precision passive parts.
Lastly, all components wanted to construct it are generic, available, and low-cost! Whole components value is ~$10, whereas against this the same pace AD652, by itself, prices ~$40.
Stephen Woodward‘s relationship with EDN’s DI column goes again fairly a methods. In all, a complete of 64 submissions have been accepted since his first contribution was revealed in 1974.
Associated Content material